Modern microprocessors allow storing of integers in a packed format such that one processor register holds several packed integers. Packed integer operations then operate on each packed integer in the processor register. Many architectures include special instructions for packing integers and dealing with packed integer values, such as the x86 MMX, SSE, and AVX instructions, among others. Packed integers are often truncated representations of integer values. For example, packing often includes storing 32-bit integer values using 16 bits or 16-bit integer values using 8 bits.
For example, the x86 PACKSSWB instruction packs 16-bit word signed integer values in 8-bit signed integer values. The x86 PACKSSDW instruction packs 32-bit double-word signed integer values into 16-bit signed integers. Both instructions are defined to detect signed saturation, and to indicate signed saturation by placing a particular value in a packed integer result.
Saturation occurs when an integer is too large or small to be represented when packed as a smaller number of bits. For example, some signed 32-bit numbers are too large or too small to be stored using 16 bits. Also, some unsigned 32-bit numbers are too large to be stored using 16 bits. When packing integers, saturation may result in incorrect operation, so it is necessary to detect and indicate that saturation has occurred.
Typically, the same processor registers are used for both 32-bit and 16-bit packing operations. For example, x86 XMM registers can hold several 32-bit values, or twice as many 16-bit values. Microprocessor designers strive to use gates efficiently for each function of the processor to reduce area and power consumption and meet timing constraints. A solution is needed that detects saturation of packed integers of multiple widths using a single module with an efficient configuration of processor logic gates.